IDT82V3010PVG【PDF 9/31 页】IC PLL WAN 51/E1/OC3 DUAL 56SSOP

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IDT82V3010

T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

Measures of Performance

Feberuary 20, 2009

period. Usually, the given timing signal and the ideal timing signal are of

the same frequency. Phase continuity applies to the output of the

synchronizer after a signal disturbance due to a mode change. The

observation period is usually the time from the disturbance, to just after

the synchronizer has settled to a steady state.

In the case of the IDT82V3010, the output signal phase continuity is

maintained to within ±5 ns at the instance (over one frame) of all mode

changes. The total phase shift, depending on the type of mode change,

may accumulate up to 200 ns over many frames. The rate of change of

the 200 ns phase shift is limited to a maximum phase slope of

approximately 5 ns per 125 s. This meets the AT&T TR62411

maximum phase slope requirement of 7.6 ns per 125 s.

3.12

PHASE LOCK TIME

This is the time it takes the synchronizer to phase lock to the input

signal. Phase lock occurs when the input signal and output signal are

not changing in phase with respect to each other (not including jitter).

Lock time is very difficult to determine because it is affected by many

factors including:

1. Initial input to output phase difference

2. Initial input to output frequency difference

3. Synchronizer loop filter

4. Synchronizer limiter

Although a short lock time is desirable, it is not always possible to

achieve due to other synchronizer requirements. For instance, better

jitter transfer performance is achieved with a lower frequency loop filter

which increases lock time. And better (smaller) phase slope

performance (limiter) results in longer lock times. The IDT82V3010 loop

filter and limiter are optimized to meet the AT&T TR62411 jitter transfer

and phase slope requirements. Consequently, phase lock time, which is

not a standard requirement, may be longer than in other applications.

See “7.1 Performance”for details.

The IDT82V3010 provides a FLOCK pin to enable the Fast Lock

mode. When this pin is set to high, the DPLL will lock to an input

reference within approximately 500 ms.

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IDT82V3010PVG8 功能描述:IC PLL WAN 51/E1/OC3 DUAL 56SSOP RoHS:是类别:集成电路 (IC) >> 时钟/计时 - 专用系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装封装/外壳:28-SSOP（0.209"，5.30mm 宽）供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT

IDT82V3011 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3011PV 制造商:INT_DEV_TECH 功能描述:

IDT82V3011PVG 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是类别:集成电路 (IC) >> 时钟/计时 - 专用系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装封装/外壳:28-SSOP（0.209"，5.30mm 宽）供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT

IDT82V3011PVG8 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是类别:集成电路 (IC) >> 时钟/计时 - 专用系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装封装/外壳:28-SSOP（0.209"，5.30mm 宽）供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT

IDT82V3012 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012PV 制造商:Integrated Device Technology Inc 功能描述:

IDT82V3012PVG 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是类别:集成电路 (IC) >> 时钟/计时 - 专用系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是主要目的:存储器，RDRAM 输入:晶体输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装封装/外壳:16-TSSOP（0.173"，4.40mm 宽）供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6

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